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VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
MK2069-01
IDT VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
1
MK2069-01
REV K 051310
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable, jittery
input clock and provide a de-jittered, low phase noise
output clock at a user determined frequency. The device’s
clock multiplication ratios are user selectable since all major
PLL divider blocks can be configured through device pin
settings. External PLL loop filter components allow tailoring
of the VCXO PLL loop response and therefore the clock
jitter attenuation characteristics.
The MK2069-01 is ideal for line card applications. Its three
input MUX enables selection of the master or slave
(backup) system clocks, as well as a backup local line card
clock. The lock detector (LD) output serves as a clock
status monitor. The clear (CLR) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR also serves as a temporary holdover function when
kept low.
Features
Input clock frequency of 1 kHz to 170 MHz
Output clock frequency of 500 kHz to 160 MHz
Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
selection of external loop filter components.
3:1 Input MUX for input reference clocks
PLL lock status output
PLL Clear function allows seamless synchronizing to an
altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
VCXO-based clock generation offers very low jitter and
phase noise generation, even with a low frequency or
jittery input clock.
2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies (TCLK).
Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
56 pin TSSOP package
Single 3.3 V power supply
5 V tolerant inputs on ICLK0 and ICLK1
Block Diagram
C harge
Pum p
VC XO
P u lla b le
xtal
VC LK
X2
X1
ISET
4
VD D
4
CL R
LF
FV D iv ide r
1-4096
RV
Div id e r
1 ,2,4,1 2 8
SV
Div id e r
1,2 ,4,6,8,
10,12,16
IC L K 2
IC L K 1
MX 1 :0
0X
RV 1 :0
2
RT
Div id e r
1-4
Ph ase
De te cto r
VC XO
PLL
FT D iv ide r
1-64
ST
Div id e r
2,4 ,8,1 6
VC O
T ran slato r
PL L
SV 2 :0
3
F V 11:0
FT5 :0
6
ST1 :0
2
TC LK
OE V
OE T
IC L K 0
10
01
2
LD
OE L
GN D
RCL K
OE R
Lo c k D e tector
12
LD C
LD R
LF R
RT 1 :0
2
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